1. Field of the Invention
The invention relates to the fabrication of integrated circuits using selfpatterned thin films, and more particularly to the fabrication of integrated circuits utilizing self-patterned layered superlattice material thin films.
2. Statement of the Problem
As is well-known, integrated circuits (ICs) are fabricated by layering and patterning thin films on a substrate, such as a silicon or gallium arsenide wafer. The patterning process is a complicated and expensive one that normally requires the application of a photo resist layer, exposure of the resist through a mask to define the device pattern, etching to remove portions of the thin film materials, and removal of the remaining resist in a solvent wash.
It is known that some materials, such as PZT, may be self-patterned, thereby eliminating the need for some of the photo-resist and etching steps. See, Yuichi Nakao, et. al., Micro-Patterning of PbZr.sub.x Ti.sub.1-x O.sub.3 Thin Films Prepared by Photo Sensitive Sol-Gel Solutions, Jpn. J. Appl. Phs. Vol. 32, Part 1, No. 9B, pp. 4141-4143, September 1993 and Soyama et al., The Formation of a Fine-Patterned Ferroelectric Thin-Film From a Sol-Gel Solution Containing a Photo-Sensitive Water Generator, Proceedings Of The International Symposium On Applied Ferroelectrics (1994). In this self-patterning method, a photo-sensitive sol-gel solution is applied to a substrate and exposed to UV radiation through a mask. The UV radiation causes reactions that accelerate polymerization in the areas exposed to the radiation. The mask prevents polymerization of selected portions of the film by blocking ultraviolet radiation. The exposed substrate is then developed by washing it to remove the unpolymerized portions, thereby leaving a fine micro pattern over the area that was polymerized by exposure to ultraviolet radiation. The micro pattern consists of a polymerized PZT film that is insoluble in the developing solution. The patterned thin film is then annealed to form a solid PZT pattern.
While the above process is an important advance in the art, there remains a problem in applying the process to the fabrication of integrated circuits. Conventional integrated processes are not compatible with a self-patterned thin film of a material such as PZT. For example, PZT is easily damaged by etches that are used to pattern subsequent layers, such as the interlayer dielectrics, and the self-patterning process leaves it exposed to such etches. Thus, the self-patterning process and materials cannot be used in conventional integrated fabrication processes without further advances in the art.
Recently, interest in the ferroelectric field has shifted to a new class of materials, called layered superlattice materials, which have been found to be far superior to PZT for ferroelectric uses. See for example, U.S. Pat. No. 5,519,234 issued May 21, 1996. These materials are more complex than PZT; while PZT is a solid solution of two ABO.sub.3 type perovskites, layered superlattice materials are materials that spontaneously form complex crystal structures having collated intergrowth layers. Thus, they are more difficult to form than PZT and are more susceptible to damage by conventional integrated circuit processing. Moreover, some of the elements contained in the layered superlattice materials can be damaging to semiconductors and other materials, such as silicon, conventionally used in integrated circuits. Thus, if the advances represented by the discovery of the superior properties of the layered superlattice are to be utilized in a self-patterning integrated circuit fabrication process, there is a need both for a self-patterning process that produces high quality layered superlattice materials and for an integrated circuit fabrication process that permits such a self-patterned material to be successfully utilized in combination with the more conventional materials and processes in the integrated circuit art.